1. Field of the Invention
The present invention relates to an information processing device, and more particularly, to an information processing device connected to another information processing device for communicating information therewith.
2. Description of the Related Art
In many portable information processing devices, battery is used as their power supply. To prolong the life of the battery, therefore, a method of preventing waste of electric power is generally known wherein the system is set in a standby state when it is not required to process information.
To set the system in the standby state, a method of stopping the supply of a clock signal, for example, is well known.
FIG. 20 shows an example of such a conventional information processing device. In the example shown in the figure, information processing devices 10 and 30 are interconnected by a bus 20 to constitute a system.
The information processing device 10 comprises a CPU (Central Processing Unit) 11, a clock control circuit 12, a main circuit 13, a communication circuit 14, and a memory 15. The device 10 processes information exchanged with the information processing device 30 through the bus 20, and when there is no information to be processed, the CPU 11 causes the clock control circuit 12 to stop the generation of a clock signal, to thereby reduce the consumption of power.
The CPU 11 controls the individual parts of the device in accordance with programs and data stored in the memory 15, and also performs a variety of information processing.
The clock control circuit 12 starts or stops the generation of the clock signal under the control of the CPU 11.
The main circuit 13 comprises, for example, an interface circuit etc.
The communication circuit 14 carries out data conversion and protocol conversion when exchanging information with the information processing device 30 through the bus 20.
The memory 15 comprises a semiconductor memory such as a RAM (Random Access Memory), for example, and temporarily stores programs executed by the CPU 11 as well as data.
On the other hand, the information processing device 30 comprises a CPU 31, a clock control circuit 32, a main circuit 33, a communication circuit 34, and a memory 35.
The CPU 31 controls the individual parts of the device in accordance with programs and data stored in the memory 35, and also performs a variety of information processing.
The clock control circuit 32 starts or stops the generation of a clock signal under the control of the CPU 31.
The main circuit 33 comprises, for example, an interface circuit etc.
The communication circuit 34 carries out data conversion and protocol conversion when exchanging information with the information processing device 10 through the bus 20.
The memory 35 comprises a semiconductor memory such as a RAM, for example, and temporarily stores programs executed by the CPU 31 as well as data.
Operation of the conventional device configured as above will be now described.
While the device is operating normally, the CPU 11 instructs the clock control circuit 12 to supply a clock signal, and therefore, the clock control circuit 12 generates and supplies a clock signal to the individual parts of the device.
On the other hand, when the device is switched to the standby state, the CPU 11 requests the clock control circuit 12 to stop the generation of the clock signal. As a result, the clock control circuit 12 stops generating the clock signal, so that the main circuit 13, the communication circuit 14 and the memory 15 are brought to a stopped state, whereby the consumption of electric power can be restrained.
FIG. 21 shows an example of another conventional device. In the example shown in the figure, the information processing device 10 is additionally provided with an external interrupt circuit 16. In other respects, the device is configured in the same manner as the counterpart shown in FIG. 20.
The external interrupt circuit 16 is always supplied with power and thus is capable of operation. When input with an interrupt signal from the information processing device 30 while the information processing device 10 is in the standby state, the external interrupt circuit accepts the interrupt request and wakes the CPU 11 up to resume normal operation.
Specifically, if, while the information processing device 10 is in the standby state, a request occurs in the information processing device 30 for a certain process to be executed by the information processing device 10, the information processing device 30 generates an interrupt signal with respect to the information processing device 10.
Consequently, the external interrupt circuit 16 of the information processing device 10 supplies a wakeup signal to the CPU 11. On receiving the wakeup signal, the CPU 11 requests the clock control circuit 12 to restart the generation of the clock signal. As a result of the request, the clock control circuit 12 restarts to generate the clock signal, whereupon the information processing device 10 switches from the standby state to the normal state.
In the conventional device shown in FIG. 20, when the information processing device 10 is in the standby state, the communication circuit 14 also is in the stopped state. A problem therefore arises in that a request for a process, if occurred in the information processing device 30, cannot be accepted.
In the example shown in FIG. 21, when the device 10 is in the standby state, the generation of the clock signal is stopped by the clock control circuit 12, and accordingly, the external interrupt circuit 16 operates asynchronously with the clock signal when looking up the state of the signal supplied from the communication circuit 34 to recognize the generation of an interrupt and supplying the wakeup signal to the CPU 11. Because of the operation asynchronous with the clock signal, therefore, malfunction can be caused by noise superposed on the bus 20.
Also, since there is a time lag from the acceptance of the interrupt signal until the clock control circuit 12 actually starts to supply the clock signal, a problem arises in that the first data transmitted from the information processing device 30 may fail to be received.